Echo cancelers are now commonly used to cancel echoes in communication circuits. As echo delay path in a communication circuit can be quite long resulting in a long delay interval, for example, 64 milliseconds. Additionally, the echo delay path may vary substantially from one communication circuit to another. Therefore, a transversal filter used in the echo canceler must be capable of modeling an impulse response characteristic including the 64 millisecond delay. Consequently, the number of so-called taps and associated processing circuitry required in the transversal filter becomes quite large. For example, if the echo canceler sampling rate K.sup.-1 is 8 kHz , 512 taps are required to model a 64 millisecond impulse response. Therefore, the resulting echo canceler is complex and expensive to implement. Moreover, as the number of taps increases the time to converge the impulse response to a desired quality also increases because of the processing complexity. Otherwise, the echo canceler may become unstable.
One attempt at overcoming the problems associated with a large number of taps in an echo canceler is disclosed in U.S. Pat. No. 3,721,777 issued to E. J. Thomas on Mar. 20, 1973. In this prior arrangement, a so-called "short" echo canceler is connected in series with an adjustable delay unit across the echo delay path. A delay estimator is also connected across the echo delay path for generating an estimate of the delay by cross correlating a received signal and a resulting echo signal in the echo path and, accordingly, adjusting the adjustable delay. However, the delay estimator requires a delay line having a number of taps and associated multipliers and integrators equal to that which an equivalent echo canceler would need. Therefore, there is no savings in processing complexity over an individual "long" echo canceler and, apparently, savings would only result if the delay estimator was multiplexed with a large number of the short canceler and delay unit combinations.